Electronic device

ABSTRACT

An electronic device including a semiconductor memory The semiconductor memory includes one or more resistive storage cells; at least one reference resistance block including at least two reference resistance transistors which are coupled in series; a data sensing block suitable for comparing resistance values of a resistive storage cell selected among the one or more resistive storage cells and the reference resistance block, and sensing data of the selected resistive storage cell; and a reference resistance adjustment block suitable for adjusting the resistance value of the reference resistance block by adjusting gate voltages of the reference resistance transistors.

CROSS-REFERENCE TO RELATED APPLICATION

This patent document claims priority of Korean Patent Application No. 10-2016-0141894, entitled “ELECTRONIC DEVICE” and filed on Oct. 28, 2016, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

This patent document relates to memory circuits or devices and their applications in electronic devices or systems.

BACKGROUND

Recently, as electronic appliances trend toward miniaturization, low power consumption, high performance, multi-functionality, and so on, semiconductor devices capable of storing information in various electronic appliances such as a computer, a portable communication device, and so on have been demanded in the art, and research has been conducted for the semiconductor devices. Such semiconductor devices include semiconductor devices which can store data using a characteristic that they are switched between different resistance states according to an applied voltage or current, for example, an RRAM (resistive random access memory), a PRAM (phase change random access memory), an FRAM (ferroelectric random access memory), an MRAM (magnetic random access memory), an E-fuse, etc.

SUMMARY

The disclosed technology in this patent document includes memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device in which a reference resistance block includes at least two transistors coupled in series such that a reference resistance value as a reference for data sensing is adjusted precisely depending on a temperature.

In one aspect, an electronic device including a semiconductor memory is provided such that the semiconductor memory comprises: one or more resistive storage cells; at least one reference resistance block including at least two reference resistance transistors which are coupled in series; a data sensing block suitable for comparing resistance values of a resistive storage cell selected among the one or more resistive storage cells and the reference resistance block, and sensing data of the selected resistive storage cell; and a reference resistance adjustment block suitable for adjusting the resistance value of the reference resistance block by adjusting gate voltages of the reference resistance transistors.

In an implementation, an electronic device may include a semiconductor memory, the semiconductor memory including: one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block.

Implementations of the above electronic device may include one or more the following.

The data sensing block may include a first input terminal through which a read current flows to the selected resistive storage cell and a second input terminal through which a reference current flows to the reference resistance block. The reference resistance adjustment block applies a bias voltage to a gate of at least one first reference resistance transistor of the at least two reference resistance transistors, and adjusts the gate voltage of at least one second reference resistance transistor of the at least two reference resistance transistors. The reference resistance adjustment block adjusts, depending on a temperature, the gate voltage of at least one first reference resistance transistor of the at least two reference resistance transistors and the gate voltage of at least one second reference resistance transistor of the at least two reference resistance transistors, and individually adjusts the gate voltage of the at least one first reference resistance transistor and the gate voltage of the at least one second reference resistance transistor. The first gate voltage may include a bias voltage, and the second gate voltage may include an adjustment voltage adjusted depending on a temperature. The first gate voltage may include a first adjustment voltage adjusted depending on a temperature, and the second gate voltage may include a second adjustment voltage adjusted depending on a temperature. The reference resistance adjustment block may include: a voltage generation unit structured to generate a voltage of which level is adjusted depending on a temperature; and a trimming unit coupled to the voltage generation unit to receive the voltage and operable to generate the adjustment voltage by dividing the voltage by a division ratio that is determined based on voltage adjustment codes. The reference resistance adjustment block may include: a first voltage generation unit to generate a first voltage of which level is adjusted depending on a temperature; a first trimming unit coupled to the first voltage generation unit to receive the first voltage and to generate the first adjustment voltage by dividing the first voltage by a first division ratio that is determined based on first voltage adjustment codes; a second voltage generation unit to generate a second voltage of which level is adjusted depending on a temperature; and a second trimming unit coupled to the second voltage generation unit to receive the second voltage and to generate the second adjustment voltage by dividing the second voltage by a second division ratio that is determined based on second voltage adjustment codes. The semiconductor memory may further include: first and second transistors coupled in series between the first input terminal and the one or more resistive storage cells, and turned on or off in response to a read enable signal and a clamp signal, respectively; and third and fourth transistors coupled in series between the second input terminal and the reference resistance block, and turned on or off in response to the read enable signal and the clamp signal, respectively. Each resistive storage cell comprises: a selection element; and a variable resistance element structured to be operable to exhibit different resistance values that represent different data stored in the resistive storage cell. The variable resistance element comprises a metal oxide or a structure in which a tunnel barrier layer is interposed between two ferromagnetic layers. The reference resistance block may further include at least one third reference resistance transistor, and the first reference resistance transistor, the second reference resistance transistor and the third reference resistance transistor are coupled in series, and the reference resistance adjustment block may provide a third gate voltage to the third reference resistance transistor. The first gate voltage may include a first adjustment voltage adjusted depending on a temperature, and the second gate voltage may include a second adjustment voltage adjusted depending on a temperature, and the third gate voltage includes a bias voltage.

The electronic device may further include a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory is part of the memory unit in the microprocessor.

The electronic device may further include a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.

The electronic device may further include a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.

The electronic device may further include a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.

The electronic device may further include a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.

In another aspect, an electronic device including a semiconductor memory is provided. The semiconductor memory may comprise a plurality of bit lines and a plurality of source lines; a plurality of resistive storage cells coupled between a corresponding bit line and a corresponding source line among the plurality of bit lines and the plurality of source lines; a plurality of reference bit lines and a plurality of reference source lines; a plurality of reference resistance blocks coupled between a corresponding reference bit line and a corresponding reference source line among the plurality of reference bit lines and the plurality of reference source lines, and each including a first reference resistance transistor and a second reference resistance transistor that are coupled in series; a plurality of data sensing blocks each comparing a read current flowing through a corresponding bit line among the plurality of bit lines and a reference current flowing through a corresponding reference bit line among the plurality of reference bit lines to determine data stored in a resistive storage cell selected among a plurality of resistive storage cells coupled to the corresponding bit line; and a reference resistance adjustment block adjusting resistance values of the reference resistance blocks by adjusting gate voltages of the reference resistance transistors. In an implementation, an electronic device may include a semiconductor memory, the semiconductor memory including: a plurality of bit lines and a plurality of source lines; a plurality of resistive storage cells coupled between a corresponding bit line and a corresponding source line among the plurality of bit lines and the plurality of source lines; a plurality of reference bit lines and a plurality of reference source lines; a plurality of reference resistance blocks coupled between a corresponding reference bit line and a corresponding reference source line among the plurality of reference bit lines and the plurality of reference source lines, and each including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a plurality of data sensing blocks each comparing a read current flowing through a corresponding bit line among the plurality of bit lines and a reference current flowing through a corresponding reference bit line among the plurality of reference bit lines to determine data stored in a resistive storage cell selected among a plurality of resistive storage cells coupled to the corresponding bit line; and a reference resistance adjustment block coupled to the reference resistance blocks and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust resistance values of the reference resistance blocks.

Implementations of the above electronic device may include one or more the following.

The plurality of data sensing blocks may include first and second input terminals, and the semiconductor memory may further include: a plurality of first and second transistors coupled in series between the first input terminals of the data sensing blocks and the bit lines, and turned on or off in response to a read enable signal and a clamp signal, respectively; and a plurality of third and fourth transistors coupled in series between the second input terminals of the data sensing blocks and the reference bit lines, and turned on or off in response to the read enable signal and the clamp signal, respectively. The reference resistance adjustment block applies a bias voltage to a gate of the first reference resistance transistor, and provides a gate voltage to the second reference resistance transistor. The reference resistance adjustment block is structured to render the gate voltages provided to the first and second reference resistance transistors to depend on a temperature. The first gate voltage may include a bias voltage, and the second gate voltage include an adjustment voltage adjusted depending on a temperature. The first gate voltage may include a first adjustment voltage adjusted depending on a temperature, and the second gate voltage may include a second adjustment voltage adjusted depending on a temperature. The reference resistance adjustment block may include: a voltage generation unit to a voltage of which level is adjusted depending on a temperature; and a trimming unit coupled to the voltage generation unit to receive the voltage and operable to generate the adjustment voltage by dividing the voltage by a division ratio that is determined based on voltage adjustment codes. Each reference resistance adjustment block may include: a first voltage generation unit operable to generate a first voltage of which level is adjusted depending on a temperature; a first trimming unit coupled to the first voltage generation unit to receive the first voltage and operable to generate the first adjustment voltage by dividing the first voltage by a division ratio that is determined based on first voltage adjustment codes; a second voltage generation unit operable to generate a second voltage of which level is adjusted depending on a temperature; and a second trimming unit coupled to the second voltage generation unit to receive the second voltage and operable to generate the second adjustment voltage by dividing the second voltage by a division ratio that is determined based on second voltage adjustment codes. Each reference resistance block may further include at least one third reference resistance transistor, and the first reference resistance transistor, the second reference resistance transistor and the third reference resistance transistor may be coupled in series, and the reference resistance adjustment block may provide a third gate voltage to the third reference resistance transistor. The first gate voltage may include a first adjustment voltage adjusted depending on a temperature, and the second gate voltage may include a second adjustment voltage adjusted depending on a temperature, and the third gate voltage may include a bias voltage. Each resistive storage cell comprises: a selection element; and a variable resistance element structured to be operable to exhibit different resistance values that represent different data stored in the resistive storage cell. The variable resistance element comprises a metal oxide or a structure in which a tunnel barrier layer is interposed between two ferromagnetic layers.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing an example of a magnetic tunnel junction (MTJ) as one of structures in which a tunnel barrier layer is interposed between two ferromagnetic layers.

FIGS. 2A and 2B are views explaining a principle of storing data in a variable resistance element 210.

FIG. 3 is a configuration diagram illustrating a memory circuit (device) including variable resistance elements in accordance with an implementation of the present disclosure.

FIG. 4 is a configuration diagram illustrating a memory circuit (device) including variable resistance elements in accordance with an implementation of the present disclosure.

FIG. 5 is a configuration diagram illustrating a memory circuit (device) including variable resistance elements in accordance with an implementation of the present disclosure.

FIG. 6 is a representation of an example of a graph to assist in the explanation of changes in the resistance value of a variable resistance element R depending on the state of the variable resistance element R and the voltage applied to both ends of the variable resistance element R.

FIG. 7 is of representations of examples of graphs to assist in the explanation of changes in the resistance values of reference resistance blocks depending on changes of an adjustment voltage VCON when the reference resistance blocks have various shapes, respectively.

FIG. 8 is a configuration diagram illustrating a reference resistance adjustment block 530 in accordance with an implementation of the present disclosure.

FIG. 9 is a configuration diagram illustrating a voltage generation unit 810 in accordance with an implementation of the present disclosure.

FIG. 10 is a configuration diagram illustrating a trimming unit 820 in accordance with an implementation of the present disclosure.

FIG. 11 is a configuration diagram illustrating a memory circuit (device) including variable resistance elements in accordance with an implementation of the present disclosure.

FIG. 12 is a configuration diagram illustrating a reference resistance adjustment block 1130 in accordance with an implementation of the present disclosure.

FIG. 13 is a configuration diagram illustrating a memory circuit (device) including variable resistance elements in accordance with an implementation of the present disclosure.

FIG. 14 is a configuration diagram illustrating a memory circuit (device) including variable resistance elements in accordance with an implementation of the present disclosure.

FIG. 15 is a configuration diagram illustrating a memory circuit (device) including variable resistance elements in accordance with an implementation of the present disclosure.

FIG. 16 is a configuration diagram illustrating a memory circuit (device) including variable resistance elements in accordance with an implementation of the present disclosure.

FIG. 17 is a configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

FIG. 18 is a configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

FIG. 19 is a configuration diagram of a system implementing memory circuitry based on the disclosed technology.

FIG. 20 is a configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

FIG. 21 is a configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

DETAILED DESCRIPTION

Various examples and implementations of the disclosed technology are described below in detail with reference to the accompanying drawings.

A semiconductor memory device in accordance with implementations of the disclosed technology may include a variable resistance element that exhibits a variable resistance characteristic that allows to have different resistance states of different resistance values for representing different data for data storage. A resistance state of the variable resistance element may be changed by applying a voltage or current of a sufficient magnitude in a data write operation. Therefore, the variable resistance element is capable of storing different data. In implementations, such a variable resistance element may include a single layer or a multi-layer that exhibits the variable resistance characteristic and includes a material used in a RRAM, PRAM, STTRAM, MRAM or FRAM (e.g., a ferromagnetic material), a ferroelectric material, a phase change material such as a chalcogenide material, a metal oxide such as a perovskite material, and/or a transition metal oxide.

The variable resistance element may include a metal oxide, e.g., a transition metal oxide such as a nickel (Ni) oxide, a titanium oxide (TiO), a hafnium oxide (HfO), a zirconium oxide (ZrO), a tungsten oxide (WO) or a cobalt oxide (CoO), and/or a perovskite material such as a strontium titanium oxide (STO: SrTiO) and/or a praseodymium calcium manganese oxide (PCMO: PrCaMnO).

Moreover, the variable resistance element may include a phase change material. The phase change material may include a chalcogenide material such as germanium-antimony-tellurium (GST: GeSbTe). The variable resistance element switches between different resistance states by changing a crystal state or an amorphous state using a heat.

The variable resistance element may include two magnetic layers and a tunnel barrier layer interposed between the two magnetic layers. The magnetic layer may include nickel-ferrum-cobalt (NiFeCo) or Cobalt-ferrum (CoFe), etc. The tunnel barrier layer may include aluminum oxide Al₂O₃. The variable resistance element may switch between two different resistance states according to a magnetization direction of the magnetic layer. For example, the variable resistance element may be in a low resistance state when a magnetization direction of two magnetic layers is parallel, and be in a high resistance state when a magnetization direction of two magnetic layers is anti-parallel.

FIG. 1 is a diagram showing an example of a magnetic tunnel junction (MTJ) as one of structures in which a tunnel barrier layer is interposed between two ferromagnetic layers.

As shown in FIG. 1, an MTJ 100 includes a first electrode layer 110 as a top electrode, a second electrode layer 120 as a bottom electrode, a first ferromagnetic layer 112 and a second ferromagnetic layer 122 as a pair of ferromagnetic layers, and a tunnel barrier layer 130 which is formed between the pair of ferromagnetic layers 112 and 122.

The first ferromagnetic layer 112 may be or include a free ferromagnetic layer of which magnetization direction may be changed depending on the direction of the current applied to the MTJ 100, and the second ferromagnetic layer 122 may be or include a pinned ferromagnetic layer of which magnetization direction is pinned to a fixed direction.

Such an MTJ 100 can be controlled to change its resistance value depending on the direction of the current at a sufficiently high magnitude and this property can be used for storing different data such as “0” or “1.”

FIGS. 2A and 2B are views explaining a principle of storing data in a variable resistance element 210. The variable resistance element 210 may be or include the MTJ 100 described above with reference to FIG. 1.

First, FIG. 2A is a diagram explaining a principle of recording data with a low logic value in the variable resistance element 210. In order to select the variable resistance element 210 to store data, a word line 230 electrically coupled to the variable resistance element 210 is activated, and a transistor 220 is turned on. This can be achieved by turning on the transistor 220 coupled to the variable resistance element 210 under an applied voltage at the word line 230 coupled to the gate of the transistor 220 in the example shown in FIG. 2A. Once the transistor 220 is turned on, a current can be directed to flow from one end 251 toward the other end 252 (in the direction indicated by the arrow), that is, from the first electrode layer 110 as the top electrode of the MTJ 100 shown in FIG. 1 to the second electrode layer 120 as the bottom electrode, the magnetization direction of the first ferromagnetic layer 112 as the free ferromagnetic layer and the magnetization direction of the second ferromagnetic layer 122 as the pinned ferromagnetic layer become parallel to each other, and the variable resistance element 210 has a low resistance state. When the variable resistance element 210 is the low resistance state, it is defined that ‘low’ data is stored in the variable resistance element 210.

Next, FIG. 2B is a diagram explaining a principle of recording data with a high logic value in the variable resistance element 210. In a similar manner, the word line 230 coupled to the transistor 220 which is electrically coupled to the variable resistance element 210 is activated, and the transistor 220 is turned on. As a current flows from the other end 252 toward one end 251 (in the direction indicated by the arrow), that is, from the second electrode layer 120 to the first electrode layer 110, the magnetization direction of the first ferromagnetic layer 112 and the magnetization direction of the second ferromagnetic layer 122 become anti-parallel to each other, and the variable resistance element 210 has a high resistance state. When the variable resistance element 210 is the high resistance state, it is defined that ‘high’ data is stored in the variable resistance element 210.

The logic value of the data stored in the variable resistance element 210 is changed depending on the resistance value of the variable resistance element 210. In the case where the difference between the resistance values of the high resistance state and the low resistance state of the variable resistance element 210 is great, it is easy to determine the data stored in the variable resistance element 210. In the case where the difference between the resistance values of the high resistance state and the low resistance state of the variable resistance element 210 is small, it is difficult to determine the data stored in the variable resistance element 210, and thus, the probability of an error to occur in discriminating data increases. Therefore, a technology capable of precisely discriminating the data stored in a variable resistance element even when the difference between the resistance values of the high resistance state and the low resistance state of the variable resistance element is small is demanded in the art.

FIGS. 3, 4, 5, 11, 13, 14, 15 and 16 illustrate implementations of memory circuits (devices) which have variable resistance elements as described above.

FIG. 3 is a configuration diagram illustrating a representation of an example of a memory circuit (device) including variable resistance elements.

Referring to FIG. 3, the memory circuit (device) may include a plurality of data sensing blocks 310_0 to 310_n (n is a natural number), a plurality of read enable transistors RT1 and RT2, a plurality of clamp transistors CT1 and CT2, and a plurality of reference resistance elements REF_R.

Each of the plurality of data sensing blocks 310_0 to 310_n may include first and second input terminals I1 and I2. The first input terminal I1 may be coupled with a cell path CELL PATH through the read enable transistor RT1 and the clamp transistor CT1, and the second input terminal I2 may be coupled with the reference resistance element REF_R through the read enable transistor RT2 and the clamp transistor CT2.

The read enable transistors RT1 and RT2 may be turned on when a read enable signal REN which is activated in a read operation period is activated, and be turned off when the read enable signal REN is deactivated. The clamp transistors CT1 and CT2 may be turned on when a clamp signal CLAMP is activated, and be turned off when the clamp signal CLAMP is deactivated. Depending on the voltage level of the clamp signal CLAMP, the amounts of the currents flowing through first and second input terminals I1 and I2 may be adjusted.

The cell path CELL PATH may be or include a path which is coupled with a resistive storage cell selected among a plurality of resistive storage cells (not shown in FIG. 4). In a read operation, a read current IRD may flow through the first input terminal I1 and the cell path CELL PATH.

The reference resistance element REF_R may have a resistance value serving as a reference for sensing the data of the selected resistive storage cell. In the read operation, a reference current IREF may flow between the second input terminal I2 and the reference resistance element REF_R.

In the read operation, the data sensing blocks 310_0 to 310_n may compare the currents IRD and IREF flowing respectively through the first and second input terminals I1 and 12 to determine data. The data sensing blocks 310_0 to 310_n may amplify the data determined and output the data of selected resistive storage cells included in the cell paths CELL PATH as outputs D0 to Dn. For example, assume that a variable resistance element has a low resistance state when data bit “0” is stored in a resistive storage cell and has a high resistance state when data bit “1” is stored in the resistive storage cell. The data sensing blocks 310_0 to 310_n may provide outputs D0 to Dn with data bit “0” for each resistive storage cell when the current amount of the read current IRD is greater than the current amount of the reference current IREF. The data sensing blocks 310_0 to 310_n may provide outputs D⁰ to Dn with data bit “1” for each resistive storage cell when the current amount of the read current IRD is smaller than the current amount of the reference current IREF.

Because the memory circuit (device) of FIG. 3 includes the plurality of reference resistance elements REF_R corresponding to the plurality of data sensing blocks 310_0 to 310_n, respectively, the area of the memory circuit (device) may increase.

FIG. 4 is a configuration diagram illustrating a representation of an example of a memory circuit (device) including variable resistance elements.

Referring to FIG. 4, the memory circuit (device) may include a plurality of data sensing blocks 410_0 to 410_n (n is a natural number), a plurality of read enable transistors RT1 and RT2, a plurality of clamp transistors CT1 and CT2, and a reference resistance element REF SR.

Each of the plurality of data sensing blocks 410_0 to 410_n may include first and second input terminals I1 and I2. The first input terminal I1 may be coupled with a cell path CELL PATH through the read enable transistor RT1 and the clamp transistor CT1, and the second input terminal I2 may be coupled with the reference resistance element REF SR through the read enable transistor RT2 and the clamp transistor CT2.

The read enable transistors RT1 and RT2 may be turned on when a read enable signal REN which is activated in a read operation period is activated, and be turned off when the read enable signal REN is deactivated. The clamp transistors CT1 and CT2 may be turned on when a clamp signal CLAMP is activated, and be turned off when the clamp signal CLAMP is deactivated. Depending on the voltage level of the clamp signal CLAMP, the amounts of the currents flowing through first and second input terminals I1 and I2 may be adjusted.

The cell path CELL PATH may be or include a path which is coupled with a resistive storage cell selected among a plurality of resistive storage cells (not shown in FIG. 4). In a read operation, a read current IRD may flow through the first input terminal I1 and the cell path CELL PATH.

The reference resistance element REF SR may have a resistance value to serve as a reference for sensing the data of the selected resistive storage cell, and be shared by the plurality of data sensing blocks 410_0 to 410_n. In the read operation, a reference current IREF may flow between the second input terminal I2 and a node NO to which the reference resistance element REF SR is coupled. Since a current IREF from each data sensing blocks 410_0 to 410_n flows into the node NO, the amount of a current ISREF flowing through the reference resistance element REF SR may be n+1 times the reference current IREF.

The data sensing blocks 410_0 to 410_n determine data stored in the respective resistive storage cells and may output data bit “0” as outputs D0 to Dn when the current amount of the read current IRD is greater than the current amount of the reference current IREF, and output data bit “1” as the outputs D0 to Dn when the current amount of the read current IRD is smaller than the current amount of the reference current IREF.

While the memory circuit (device) of FIG. 4 has an advantage that an area may be reduced because the plurality of data sensing blocks 410_0 to 410_n share the reference resistance element REF SR, a problem may be caused in that the memory circuit (device) of FIG. 4 is vulnerable to noise because the second input terminals 12 of all the data sensing blocks 410_0 to 410_n are coupled to the node NO.

FIG. 5 is a configuration diagram illustrating a representation of an example of a memory circuit (device) including variable resistance elements.

Referring to FIG. 5, the memory circuit (device) may include one or more resistive storage cells SC, read enable transistors RT1 and RT2, clamp transistors CT1 and CT2, a data sensing block 510, a reference resistance block 520, and a reference resistance adjustment block 530.

Each of the resistive storage cells SC may include a variable resistance element R and a selection element S which is coupled in series to the variable resistance element R. The variable resistance element R may be in a low resistance state in the case where ‘low’ value data is stored, and be in a high resistance state in the case where ‘high’ value data is stored. Alternatively, the variable resistance element R may be in a low resistance state in the case where ‘high’ value data is stored, and be in a high resistance state in the case where ‘low’ value data is stored. Herein below, descriptions will be made assuming that the memory circuit operates according to the former case. Selection elements S may be turned on or off in response to the voltages of a plurality of word lines WL0 to WLx (x is a natural number). For reference, for the sake of convenience in illustration, the internal configuration is illustrated for only one resistive storage cell SC. The resistive storage cells SC may be coupled between a bit line BL and a source line SL.

The read enable transistors RT1 and RT2 may be turned on when a read enable signal REN which is activated in a read operation period is activated, and be turned off when the read enable signal REN is deactivated. The clamp transistors CT1 and CT2 may be turned on when a clamp signal CLAMP is activated, and be turned off when the clamp signal CLAMP is deactivated. Depending on the voltage level of the clamp signal CLAMP, the amounts of the currents flowing through first and second input terminals I1 and I2 may be adjusted.

The reference resistance block 520 may have one end which is coupled to a reference bit line RBL and the other end which is coupled to a reference source line RSL. The reference resistance block 520 may include at least two reference resistance transistors REFT0 and REFT1 which are coupled in series. A bias voltage VBIAS may be applied to the gate of at least one reference resistance transistor of the at least two reference resistance transistors REFT0 and REFT1, and an adjustment voltage VCON may be applied to the gate of at least one reference resistance transistor of the at least two reference resistance transistors REFT0 and REFT1.

FIG. 5 illustrates the case where the bias voltage VBIAS is applied to either the reference resistance transistor REFT0 or the reference resistance transistor REFT1. In this case, the adjustment voltage VCON is applied to the other reference resistance transistor REFT1 or REFT0. For reference, FIG. 5 shows the first case where the bias voltage VBIAS is applied to the reference resistance transistor REFT0 and the adjustment voltage VCON is applied to the reference resistance transistor REFT1, and the second case (see the parentheses) where the bias voltage VBIAS is applied to the reference resistance transistor REFT1 and the adjustment voltage VCON is applied to the reference resistance transistor REFT0.

The bias voltage VBIAS may have a fixed voltage level, and be applied only in a read operation. For example, the voltage level of the bias voltage VBIAS may be 1.5 V or 1.8 V. While FIG. 5 illustrates the case where the reference resistance transistors REFT0 and REFT1 are NMOS transistors, other implementations are also possible. For example, the reference resistance transistors REFT0 and REFT1 may be configured as PMOS transistors. In some implementations, one of the reference resistance transistors REFT0 and REFT1 may be configured as an NMOS transistor, while the remainder may be configured as a PMOS transistor.

The data sensing block 510 may include the first and second input terminals I1 and I2. The first input terminal I1 may be coupled with the bit line BL through the read enable transistor RT1 and the clamp transistor CT1. The second input terminal I2 may be coupled with the reference bit line RBL through the read enable transistor RT2 and the clamp transistor CT2. In the read operation, the read enable signal REN and the clamp signal CLAMP may be activated, and the read enable transistors RT1 and RT2 and the clamp transistors CT1 and CT2 may be turned on. Accordingly, the first input terminal I1 and the bit line BL may be electrically coupled, and the second input terminal I2 and the reference bit line RBL may be electrically coupled.

In the read operation, a read current IRD may flow through the first input terminal I1, the read enable transistor RT1, the clamp transistor CT1, the bit line BL, a selected resistive storage cell SC (for example, a resistive storage cell SC corresponding to the word line WL0), and the source line SL. Moreover, a reference current IREF may flow through the second input terminal I2, the read enable transistor RT2, the clamp transistor CT2, the reference bit line RBL, the reference resistance block 520, and the reference source line RSL.

The current amount of the read current IRD may be determined depending on the resistance value of the selected resistive storage cell SC, and the current amount of the reference current IREF may be determined depending on the resistance value of the reference resistance block 520. The data sensing block 510 may compare the current amounts of the read current IRD and the reference current IREF, and provide output D with value “1” when the current amount of the read current IRD is greater than the current amount of the reference current IREF and provide output D with value “1” when the current amount of the read current IRD is smaller than the current amount of the reference current IREF.

A ground voltage may be applied to the reference source line RSL which is coupled to the reference resistance block 520, and the resistance value of the reference resistance block 520 may be adjusted by using the adjustment voltage VCON. The reference resistance adjustment block 530 may generate the adjustment voltage VCON, and adjust the voltage level of the adjustment voltage VCON depending on the operating condition of the memory circuit (device).

The reference resistance adjustment block 530 may adjust the voltage level of the adjustment voltage VCON depending on a temperature of the memory circuit (device). The reference voltage adjustment block 530 may lower the voltage level of the adjustment voltage VCON when a temperature falls, and raise the voltage level of the adjustment voltage VCON when a temperature rises. By using the reference resistance transistors REFT0 and REFT1 which are coupled in series, the resistance value of the reference resistance block 520 may be adjusted finely.

FIG. 6 is a representation of an example of a graph to explain changes in the resistance value of the variable resistance element R depending on the state of the variable resistance element R and the voltage applied to both ends of the variable resistance element R.

Referring to FIG. 6, the solid line A represents the resistance value change of the variable resistance element R depending on the voltage applied to both ends of the variable resistance element R (hereinafter, referred to as a both-end voltage VR) in the case where a temperature is a room temperature (for example, 25° C.), and the dotted line B represents the resistance value change of the variable resistance element R depending on the both-end voltage VR in the case where a temperature is a high temperature (for example, 90° C.). Also, a ‘LOW’ region represents the resistance value change of the variable resistance element R depending on the both-end voltage VR in the case where the variable resistance element R is in a low resistance state, and a ‘HIGH’ region represents the resistance value change of the variable resistance element R depending on the both-end voltage VR in the case where the variable resistance element R is in a high resistance state.

In the case where the variable resistance element R is in the low resistance state LOW, the resistance value of the variable resistance element R may be retained substantially constantly. However, in the case where the variable resistance element R is in the high resistance state HIGH, the resistance value of the variable resistance element R may be changed depending on not only a temperature but also the voltage level of the both-end voltage VR. For reference, the unit of the resistance value of the variable resistance element R is kΩ, and the unit of the both-end voltage VR is V.

FIG. 7 is of representations of examples of graphs to explain changes in the resistance values of reference resistance blocks depending on changes of an adjustment voltage VCON when the reference resistance blocks have various configurations, respectively.

Referring to FIG. 7, the graph G1 represents the resistance value of a reference resistance block 520 a according to a first example depending on the adjustment voltage VCON in the case where the reference resistance block 520 a includes one reference resistance transistor REFT, the graph G2 represents the resistance value of a reference resistance block 520 b according to a second example depending on the adjustment voltage VCON in the case where the reference resistance block 520 b includes two reference resistance transistors REFT0 and REFT1 and the same adjustment voltage VCON is applied to the gates of the two reference resistance transistors REFT0 and REFT1, and the graph G3 represents the resistance value of a reference resistance block 520 c according to a third example depending on the adjustment voltage VCON in the case where the reference resistance block 520 c includes two reference resistance transistors REFT0 and REFT1, a bias voltage VBIAS of 1.5 V is applied to the gate of the reference resistance transistor REFT0 and the adjustment voltage VCON is applied to the gate of the reference resistance transistor REFT1.

From FIG. 7, it may be seen that, when the adjustment voltage VCON varies from 1.40 V to 1.60 V, the resistance value of the reference resistance block 520 a according to the first example varies by 10.7 kΩ (ΔR1), the resistance value of the reference resistance block 520 b according to the second example varies by 11.1 kΩ (ΔR2), and the resistance value of the reference resistance block 520 c according to the third example varies by 4.5 kΩ (ΔR3). Therefore, the reference resistance block 520 c of the third example may adjust more finely the resistance value thereof by using the adjustment voltage VCON than the reference resistance blocks 520 a and 520 b of the first and second examples. Also, since a resistance change depending on a variation of the adjustment voltage VCON is relatively small, a reference current variation rate may be small under a given condition, whereby a data sensing error may be suppressed in a read operation.

The reference resistance block 520 c of the third example may have the following advantages over the reference resistance blocks 520 a and 520 b of the first and second examples.

(1) The reference resistance block 520 c of the third example can have a resistance value less dependent on a voltage change of the adjustment voltage VCON when a target resistance value is secured. Assume that a target resistance value is 50 kΩ. For the reference resistance block 520 a of the first example, the resistance value of 50 kΩ may be provided by using the one reference resistance transistor REFT included in the reference resistance block 520 a. Since the single reference resistance transistor REFT has a gate to which the adjustment voltage VCON is applied, the dependence of the reference resistance block 520 a on a change of the adjustment voltage VCON is great. For the reference resistance block 520 b of the second example, the resistance value of 50 kΩ may be provided by using the two reference resistance transistors REFT0 and REFT1. Despite the two reference resistance transistors REFT0 and REFT1, however, since both the resistance values of the two reference resistance transistors REFT0 and REFT1 are dependent on the voltage level of the adjustment voltage VCON, the reference resistance block 520 b has a relatively higher dependence on a change in the voltage level of the adjustment voltage VCON. For the reference resistance block 520 c of the third example, the resistance value of 50 kΩ may be provided by using the two reference resistance transistors REFT0 and REFT1. Unlike the reference resistance block 520 b of the second example, since the reference resistance block 520 c includes only one reference resistance transistor REFT1 dependent on the voltage level of the adjustment voltage VCON, the reference resistance block 520 c has a relatively lower dependence on a change in the voltage level of the adjustment voltage VCON.

(2) The reference resistance block 520 c of the third example allows a target resistance value to be provided in various ways by applying different voltages to the two reference resistance transistors REFT0 and REFT1. For example, in the case where a target resistance value is 50 kΩ, the target resistance value may be formed by setting the resistance values of the reference resistance transistors REFT0 and REFT1 to 40 kΩ and 10 kΩ, respectively or by setting the resistance values of the reference resistance transistors REFT0 and REFT1 to 20 kΩ and 30 kΩ, respectively.

(3) As described above in (1), because the dependence of the resistance value of the reference resistance block 520 c on a change in the voltage level of the adjustment voltage VCON is relatively small, the resistance value can be adjusted finely by adjusting the voltage level of the adjustment voltage VCON.

As discussed above, the disclosed technology provides a reference resistance block using at least two reference resistance transistors REFT0 and REFT1 which are coupled in series as a reference resistance element serving as a reference for determining the resistance value of a variable resistance element R. Also, the at least two reference resistance transistors REFT0 and REFT1 have gates to which individually adjusted voltages are applied. Accordingly, it is possible to provide a memory circuit (device) having reduced data sensing error when performing a read operation in the memory circuit (device).

FIG. 8 is a configuration diagram illustrating a representation of an example of the reference resistance adjustment block 530 in accordance with an implementation.

Referring to FIG. 8, the reference resistance adjustment block 530 may include a voltage generation unit 810 and a trimming unit 820.

The voltage generation unit 810 may generate a first voltage V1 of which voltage level is changed depending on a temperature. FIG. 9 is a configuration diagram illustrating a representation of an example of the voltage generation unit 810 in accordance with an implementation. Referring to FIG. 9, the voltage generation unit 810 may include PMOS transistors P1 and P2, NMOS transistors N1 and N2, and a resistor RCON. In some implementations, the voltage generation unit 810 may include a Widlar circuit generally known in the art. The PMOS transistor P1 may have a source to which a power supply voltage VDD is applied, a gate which is coupled to a node NO1, and a drain which is coupled to a node NO2. The PMOS transistor P2 may have a source to which the power supply voltage VDD is applied, a gate which is coupled to the node NO1, and a drain which is coupled to the node NO1. The NMOS transistor N1 may have a source to which a ground voltage VSS is applied, a gate which is coupled to the node NO2, and a drain which is coupled to the node NO2. The NMOS transistor N2 may have a source which is coupled to the resistor RCON, a gate which is coupled to the node NO2, and a drain which is coupled to the node NO1. The first voltage V1, which is the output of the voltage generation unit 810, may be the both-end voltage of the resistor RCON.

When the width-to-length ratios of the gates of the transistors N1, N2, P1 and P2 are (W/L)_N1, (W/L)_N2, (W/L)_P1 and (W/L)_P2, respectively, the first voltage V1 which has a desired voltage level depending on a temperature may be generated by adjusting the resistance value of the resistor RCON and the values of (W/L)_N1, (W/L)_N2, (W/L)_P1 and (W/L)_P2.

The trimming unit 820 may generate the adjustment voltage VCON by dividing the first voltage V1 with an appropriate division ratio depending on the values of adjustment codes TM<0:3> and TMB<0:3>.

FIG. 10 is a configuration diagram illustrating a representation of an example of the trimming unit 820 in accordance with an implementation. Referring to FIG. 10, the trimming unit 820 may include a plurality of transistors N3 to N10 and resistors R1 to R4 and RL. The transistors N3, N5, N7 and N9 and the transistors N4, N6, N8 and N10 may be turned on or off in response to the adjustment codes TM<0:3> and TMB<0:3>, respectively. The adjustment codes TMB<0> to TMB<3> may be signals which are obtained by inverting the logic values of the adjustment codes TM<0> to TM<3>.

[Table 1] shows ratios VCON/V1 of the adjustment voltage VCON and the first voltage V1 depending on the values of the adjustment codes TM<0:3> and TMB<0:3>. Values in [ ] show ratios VCON/V1 in the case where the resistance values of the resistors R1 to R4 are Ra, 2*Ra, 4*Ra and 8*Ra, respectively.

TABLE 1 TM<3> − TMB<3> − TW<0> TMB<0> VCON/V1 0000 1111 RL/(R1 + R2 + R3 + R4 + RL) [RL/(15*Ra + RL)] 0001 1110 RL/(R2 + R3 + R4 + RL) [RL/(14*Ra + RL)] 0010 1101 RL/(R1 + R3 + R4 + RL) [RL/(13 *Ra + RL)] 0011 1100 RL/(R3 + R4 + RL) [RL/(12*Ra + RL)] 0100 1011 RL/(R1 + R2 + R4 + RL) [RL/(11*Ra + RL)] 0101 1010 RL/(R2 + R4 + RL) [RL/(10*Ra + RL)] 0110 1001 RL/(R1 + R4 + RL) [RL/(9*Ra + RL)] 0111 1000 RL/(R4 + RL) [RL/(8*Ra + RL)] 1000 0111 RL/(R2 + R3 + RL) [RL/(7*Ra + RL)] 1001 0110 RL/(R1 + R3 + RL) [RL/(6*Ra + RL)] 1010 0101 RL/(R1 + R3 + RL) [RL/(5*Ra + RL)] 1011 0100 RL/(R3 + RL) [RL/(4*Ra + RL)] 1100 0011 RL/(R1 + R2 + RL) [RL/(3*Ra + RL)] 1101 0010 RL/(R2 + RL) [RL/(2*Ra + RL)] 1110 0001 RL/(R1 + RL) [RL/(1*Ra + RL)] 1111 0000 RL/RL [RL/RL]

As shown in [Table 1], the trimming unit 820 may generate the adjustment voltage VCON by dividing the first voltage V1 with various division ratios depending on the values of the adjustment codes TM<0:3> and TMB<0:3>.

FIG. 11 is a configuration diagram illustrating a representation of an example of a memory circuit (device) including variable resistance elements.

Referring to FIG. 11, the memory circuit (device) may include one or more resistive storage cells SC, read enable transistors RT1 and RT2, clamp transistors CT1 and CT2, a data sensing block 1110, a reference resistance block 1120, and a reference resistance adjustment block 1130.

Unlike the memory circuit (device) of FIG. 5, when the memory circuit (device) of FIG. 11 includes the reference resistance block 120 which includes reference resistance transistors REFT0 and REFT1, an adjustment voltage VCON0 may be applied to at least one reference resistance transistor REFT0, and another adjustment voltage VCON1 may be applied to at least one reference resistance transistor REFT1. The adjustment voltages VCON0 and VCON1 are generated by the reference resistance adjustment block 1130, and the reference resistance adjustment block 1130 may adjust individually the adjustment voltages VCON0 and VCON1.

As shown in FIG. 11, by adjusting individually the gate voltages of the reference resistance transistors REFT0 and REFT1, the resistance value of the reference resistance block 1120 can be adjusted variously.

FIG. 12 is a configuration diagram illustrating a representation of an example of the reference resistance adjustment block 1130 in accordance with an implementation.

Referring to FIG. 12, the reference resistance adjustment block 1130 may include first and second voltage generation units 1210 and 1220, and first and second trimming units 1230 and 1240.

The first voltage generation unit 1210 may generate a first voltage V1 of which voltage level is changed depending on a temperature. The first trimming unit 1230 may generate the adjustment voltage VCON0 by dividing the first voltage V1 with an appropriate division ratio depending on the values of adjustment codes TM0<0:3> and TM0B<0:3>.

Once activated, the second voltage generation unit 1220 may generate a second voltage V2 of which voltage level is changed depending on a temperature. The second trimming unit 1240 may generate the adjustment voltage VCON1 by dividing the second voltage V2 with an appropriate division ratio depending on the values of adjustment codes TM1<0:3> and TM1B<0:3>.

The first and second voltage generation units 1210 and 1220 may have the same configuration as the voltage generation unit 810 of FIG. 9. However, when the width-to-length ratios of the gates of the transistors N1, N2, P1 and P2 are designated by (W/L)_N1, (W/L)_N2, (W/L)_P1 and (W/L)_P2, respectively, the resistance value of the resistor RCON and the values of (W/L)_N1, (W/L)_N2, (W/L)_P1 and (W/L)_P2 may have different values as occasion demands. By adjusting the values of the width-to-length ratios of the gates and the resistance value of the resistor RCON, the dependence of change amounts of the first and second voltages V1 and V2 generated by the first and second voltage generation units 1210 and 1220 on a temperature may be set differently. The first and second trimming units 1230 and 1240 may have the same configuration as the trimming unit 820 of FIG. 10.

FIG. 13 is a configuration diagram illustrating a representation of an example of a memory circuit (device) including variable resistance elements.

Referring to FIG. 13, the memory circuit (device) may include one or more resistive storage cells SC, read enable transistors RT1 and RT2, clamp transistors CT1 and CT2, a data sensing block 1310, a reference resistance block 1320, and a reference resistance adjustment block 1330.

Unlike the memory circuit (device) of FIG. 5, in the memory circuit (device) of FIG. 13, the reference resistance block 1320 may include three reference resistance transistors REFT0 to REFT2 which are coupled in series. FIG. 13 illustrates a case where different adjustment voltages VCON0 and VCON1 are applied to the gates of the two reference resistance transistors REFT0 and REFT1 among the three reference resistance transistors REFT0 to REFT2, a bias voltage VBIAS is applied to the remaining reference resistance transistor REFT2 and the reference resistance adjustment block 1330 generates appropriately the adjustment voltages VCON0, VCON1 and VBIAS.

In the disclosed technology, the memory circuit (device) can be configured in various manners in terms of the designs of the reference resistance block 1320 and the reference resistance adjustment block 1330. For example, the design changes to be considered can include: the number of the reference resistance transistors included in the reference resistance block 1320, the number of reference resistance transistors to which a bias voltage is applied, the number of reference resistance transistors to which an adjustment voltage is applied, and the numbers of reference resistance transistors to which the same bias voltage and the same adjustment voltage are applied. Also, as the reference resistance adjustment block 1330 is designed to have a particular configuration, the reference resistance adjustment block 1330 may be designed to generate an appropriate adjustment voltage and bias voltage in conformity with the structure of the reference resistance block 1320.

That is to say, a reference resistance block may include at least two reference resistance transistors which are coupled in series. In this case, by providing various implementations on the reference resistance block, for example how to apply the voltages to the gates of the respective reference resistance transistors, it is possible to allow a memory circuit (device) to have a high precision of a read operation.

FIG. 14 is a configuration diagram illustrating a representation of an example of a memory circuit (device) including variable resistance elements.

Referring to FIG. 14, the memory circuit (device) may include a plurality of resistive storage cells SC, read enable transistors RT1 and RT2, clamp transistors CT1 and CT2, reference resistance blocks REFR0 to REFRx, a data sensing block 1410, and a reference resistance adjustment block 1430.

The memory circuit (device) of FIG. 14 may include the plurality of reference resistance blocks REFR0 to REFRx corresponding to the resistive storage cells SC, respectively. A plurality of bias voltages VBIAS0 to VBIASx and adjustment voltages VCON0 to VCONx may be applied to the gates of reference resistance transistors REFT0 and REFT1 included in the plurality of reference resistance blocks REFR0 to REFRx, and a corresponding bias voltage and adjustment voltage may be activated once a corresponding word line is activated.

For example, in the case where a word line WL0 is activated, only the bias voltage VBIAS0 among the plurality of bias voltages VBIAS0 to VBIASx and only the adjustment voltage VCON0 among the plurality of adjustment voltages VCON0 to VCONx may be activated.

Although it is shown in FIG. 14 that the a bias voltage is applied to the reference resistance transistor REFT0, as described above with reference to FIG. 5, a particular reference resistance transistor to which a bias voltage is applied can be changed between the reference resistance transistors REFT0 and REFT1.

The configuration of each of the reference resistance blocks REFR0 to REFRx shown in FIG. 14 may be designed in various shapes as described above with reference to FIGS. 5, 11 and 13.

FIG. 15 is a configuration diagram illustrating a representation of an example of a memory circuit (device) including variable resistance elements.

Referring to FIG. 15, the memory circuit (device) may include a plurality of resistive storage cells SC, read enable transistors RT1 and RT2, clamp transistors CT1 and CT2, reference resistance blocks REFR0 to REFRy (y is a natural number), a plurality of data sensing blocks 1510_0 to 1510_y, and a reference resistance adjustment block 1530.

The memory circuit (device) of FIG. 15 may include the plurality of reference resistance blocks REFR0 to REFRy corresponding to the plurality of data sensing blocks 1510_0 to 1510_y, respectively. The respective data sensing blocks 1510_0 to 1510_y may sense and output the data stored in selected resistive storage cells SC as outputs D0 to Dy. A bias voltage VBIAS and an adjustment voltage VCON may be applied to the gates of reference resistance transistor REFT0 and REFT1 included in the plurality of reference resistance blocks REFR0 to REFRy.

As described above with reference to FIG. 5, a bias voltage is applied to either the reference resistance transistor REFT0 or the reference resistance transistor REFT1 and it is possible that a particular reference resistance transistor to which a bias voltage is applied can be changed between the reference resistance transistors REFT0 and REFT1. The remaining reference resistance transistor other than the particular resistance is supplied with an adjustment voltage through its gate. As the particular reference resistance transistor changes between the two the reference resistance transistors REFT0 and REFT1, the reference resistance transistor to which the adjustment voltage is applied is changed accordingly.

The configuration of each of the reference resistance blocks REFR0 to REFRy shown in FIG. 15 may be designed in various manners as described above with reference to FIGS. 5, 11 and 13.

FIG. 16 is a configuration diagram illustrating a representation of an example of a memory circuit (device) including variable resistance elements.

Referring to FIG. 16, the memory circuit (device) may include a plurality of resistive storage cells SC, read enable transistors RT1 and RT2, clamp transistors CT1 and CT2, reference resistance blocks REFR00 to REFRxy, a plurality of data sensing blocks 1610_0 to 1610_y, and a reference resistance adjustment block 1630.

The memory circuit (device) of FIG. 16 may include the plurality of reference resistance blocks REFR00 to REFRxy corresponding to the plurality of data sensing blocks 1610_0 to 1610_y. The respective data sensing blocks 1610_0 to 1610_y may sense and output the data stored in selected resistive storage cells SC as outputs D0 to Dy.

The memory circuit (device) of FIG. 16 may include the plurality of reference resistance blocks REFR00 to REFRxy corresponding to the resistive storage cells SC, respectively. A plurality of bias voltages VBIAS0 to VBIASx and adjustment voltages VCON0 to VCONx may be applied to the gates of reference resistance transistors REFT0 and REFT1 included in the plurality of reference resistance blocks REFR00 to REFRxy, and a corresponding bias voltage and adjustment voltage may be activated once a corresponding word line is activated.

For example, in the case where a word line WL0 is activated, only the bias voltage VBIAS0 among the plurality of bias voltages VBIAS0 to VBIASx and only the adjustment voltage VCON0 among the plurality of adjustment voltages VCON0 to VCONx may be activated.

As described above with reference to FIG. 5, between the reference resistance transistors REFT0 and REFT1, a reference resistance transistor to which a bias voltage is applied and a reference resistance transistor to which an adjustment voltage is applied may be changed.

The configuration of each of the reference resistance blocks REFR00 to REFRxy shown in FIG. 16 may be designed in various manners as described above with reference to FIGS. 5, 11 and 13.

The memory circuits (devices) of FIGS. 5, 11, 13, 14, 15 and 16 may adjust precisely a reference resistance value depending on a temperature by using transistors as a reference resistor, thereby increasing a read margin.

In the electronic devices according to the above-described implementations, by using at least two transistors included in a reference resistance block and coupled in series, it is possible to adjust precisely a reference resistance value.

The above and other memory circuits or semiconductor devices based on the disclosed technology may be used in a range of devices or systems. FIGS. 17-21 provide some examples of devices or systems that may implement the memory circuits disclosed herein.

FIG. 17 is an example of configuration diagram of a microprocessor implementing memory circuitry based on the disclosed technology.

Referring to FIG. 17, a microprocessor 2000 may perform tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The microprocessor 2000 may include a memory unit 2010, an operation unit 2020, a control unit 2030, and so on. The microprocessor 2000 may be various data processing units such as a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP) and an application processor (AP).

The memory unit 2010 is a part which stores data in the microprocessor 2000, as a processor register, or the like. The memory unit 2010 may include a data register, an address register, a floating point register and so on. Besides, the memory unit 2010 may include various registers. The memory unit 2010 may perform the function of temporarily storing data for which operations are to be performed by the operation unit 2020, result data of performing the operations and addresses where data for performing of the operations are stored.

The memory unit 2010 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory unit 2010 may include one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block. Through this, characteristics of the memory unit 2010 may be improved. As a consequence, performance characteristics of the microprocessor 2000 may be improved.

The operation unit 2020 may perform four arithmetical operations or logical operations according to results that the control unit 2030 decodes commands. The operation unit 2020 may include at least one arithmetic logic unit (ALU) and so on.

The control unit 2030 may receive signals from the memory unit 2010, the operation unit 2020 and an external device of the microprocessor 2000, perform extraction, decoding of commands, and controlling input and output of signals of the microprocessor 2000, and execute processing represented by programs.

The microprocessor 2000 according to the present implementation may additionally include a cache memory unit 2040 which can temporarily store data to be inputted from an external device other than the memory unit 2010 or to be outputted to an external device. In this case, the cache memory unit 2040 may exchange data with the memory unit 2010, the operation unit 2020 and the control unit 2030 through a bus interface 2050.

FIG. 18 is an example of configuration diagram of a processor implementing memory circuitry based on the disclosed technology.

Referring to FIG. 18, a processor 2100 may improve performance and realize multi-functionality by including various functions other than those of a microprocessor which performs tasks for controlling and tuning a series of processes of receiving data from various external devices, processing the data, and outputting processing results to external devices. The processor 2100 may include a core unit 2110 which serves as the microprocessor, a cache memory unit 2120 which serves to storing data temporarily, and a bus interface 2130 for transferring data between internal and external devices. The processor 2100 may include various system-on-chips (SoCs) such as a multi-core processor, a graphic processing unit (GPU) and an application processor (AP).

The core unit 2110 of the present implementation is a part which performs arithmetic logic operations for data inputted from an external device, and may include a memory unit 2111, an operation unit 2112 and a control unit 2113.

The memory unit 2111 is a part which stores data in the processor 2100, as a processor register, a register or the like. The memory unit 2111 may include a data register, an address register, a floating point register and so on. Besides, the memory unit 2111 may include various registers. The memory unit 2111 may perform the function of temporarily storing data for which operations are to be performed by the operation unit 2112, result data of performing the operations and addresses where data for performing of the operations are stored. The operation unit 2112 is a part which performs operations in the processor 2100. The operation unit 2112 may perform four arithmetical operations, logical operations, according to results that the control unit 2113 decodes commands, or the like. The operation unit 2112 may include at least one arithmetic logic unit (ALU) and so on. The control unit 2113 may receive signals from the memory unit 2111, the operation unit 2112 and an external device of the processor 2100, perform extraction, decoding of commands, controlling input and output of signals of processor 2100, and execute processing represented by programs.

The cache memory unit 2120 is a part which temporarily stores data to compensate for a difference in data processing speed between the core unit 2110 operating at a high speed and an external device operating at a low speed. The cache memory unit 2120 may include a primary storage section 2121, a secondary storage section 2122 and a tertiary storage section 2123. In general, the cache memory unit 2120 includes the primary and secondary storage sections 2121 and 2122, and may include the tertiary storage section 2123 in the case where high storage capacity is required. As the occasion demands, the cache memory unit 2120 may include an increased number of storage sections. That is to say, the number of storage sections which are included in the cache memory unit 2120 may be changed according to a design. The speeds at which the primary, secondary and tertiary storage sections 2121, 2122 and 2123 store and discriminate data may be the same or different. In the case where the speeds of the respective storage sections 2121, 2122 and 2123 are different, the speed of the primary storage section 2121 may be largest. At least one storage section of the primary storage section 2121, the secondary storage section 2122 and the tertiary storage section 2123 of the cache memory unit 2120 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the cache memory unit 2120 may include one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block. Through this, characteristics of the cache memory unit 2120 may be improved. As a consequence, performance characteristics of the processor 2100 may be improved.

Although it was shown in FIG. 18 that all the primary, secondary and tertiary storage sections 2121, 2122 and 2123 are configured inside the cache memory unit 2120, it is to be noted that all the primary, secondary and tertiary storage sections 2121, 2122 and 2123 of the cache memory unit 2120 may be configured outside the core unit 2110 and may compensate for a difference in data processing speed between the core unit 2110 and the external device. Meanwhile, it is to be noted that the primary storage section 2121 of the cache memory unit 2120 may be disposed inside the core unit 2110 and the secondary storage section 2122 and the tertiary storage section 2123 may be configured outside the core unit 2110 to strengthen the function of compensating for a difference in data processing speed. In another implementation, the primary and secondary storage sections 2121, 2122 may be disposed inside the core units 2110 and tertiary storage sections 2123 may be disposed outside core units 2110.

The bus interface 2130 is a part which connects the core unit 2110, the cache memory unit 2120 and external device and allows data to be efficiently transmitted.

The processor 2100 according to the present implementation may include a plurality of core units 2110, and the plurality of core units 2110 may share the cache memory unit 2120. The plurality of core units 2110 and the cache memory unit 2120 may be directly connected or be connected through the bus interface 2130. The plurality of core units 2110 may be configured in the same way as the above-described configuration of the core unit 2110. In the case where the processor 2100 includes the plurality of core unit 2110, the primary storage section 2121 of the cache memory unit 2120 may be configured in each core unit 2110 in correspondence to the number of the plurality of core units 2110, and the secondary storage section 2122 and the tertiary storage section 2123 may be configured outside the plurality of core units 2110 in such a way as to be shared through the bus interface 2130. The processing speed of the primary storage section 2121 may be larger than the processing speeds of the secondary and tertiary storage section 2122 and 2123. In another implementation, the primary storage section 2121 and the secondary storage section 2122 may be configured in each core unit 2110 in correspondence to the number of the plurality of core units 2110, and the tertiary storage section 2123 may be configured outside the plurality of core units 2110 in such a way as to be shared through the bus interface 2130.

The processor 2100 according to the present implementation may further include an embedded memory unit 2140 which stores data, a communication module unit 2150 which can transmit and receive data to and from an external device in a wired or wireless manner, a memory control unit 2160 which drives an external memory device, and a media processing unit 2170 which processes the data processed in the processor 2100 or the data inputted from an external input device and outputs the processed data to an external interface device and so on. Besides, the processor 2100 may include a plurality of various modules and devices. In this case, the plurality of modules which are added may exchange data with the core units 2110 and the cache memory unit 2120 and with one another, through the bus interface 2130.

The embedded memory unit 2140 may include not only a volatile memory but also a nonvolatile memory. The volatile memory may include a DRAM (dynamic random access memory), a mobile DRAM, an SRAM (static random access memory), and a memory with similar functions to above mentioned memories, and so on. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), a memory with similar functions.

The communication module unit 2150 may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC) such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB) such as various devices which send and receive data without transmit lines, and so on.

The memory control unit 2160 is to administrate and process data transmitted between the processor 2100 and an external storage device operating according to a different communication standard. The memory control unit 2160 may include various memory controllers, for example, devices which may control IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), RAID (Redundant Array of Independent Disks), an SSD (solid state disk), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The media processing unit 2170 may process the data processed in the processor 2100 or the data inputted in the forms of image, voice and others from the external input device and output the data to the external interface device. The media processing unit 2170 may include a graphic processing unit (GPU), a digital signal processor (DSP), a high definition audio device (HD audio), a high definition multimedia interface (HDMI) controller, and so on.

FIG. 19 is an example of configuration diagram of a system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 19, a system 2200 as an apparatus for processing data may perform input, processing, output, communication, storage, etc. to conduct a series of manipulations for data. The system 2200 may include a processor 2210, a main memory device 2220, an auxiliary memory device 2230, an interface device 2240, and so on. The system 2200 of the present implementation may be various electronic systems which operate using processors, such as a computer, a server, a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, a digital music player, a PMP (portable multimedia player), a camera, a global positioning system (GPS), a video camera, a voice recorder, a telematics, an audio visual (AV) system, a smart television, and so on.

The processor 2210 may decode inputted commands and processes operation, comparison, etc. for the data stored in the system 2200, and controls these operations. The processor 2210 may include a microprocessor unit (MPU), a central processing unit (CPU), a single/multi-core processor, a graphic processing unit (GPU), an application processor (AP), a digital signal processor (DSP), and so on.

The main memory device 2220 is a storage which may temporarily store, call and execute program codes or data from the auxiliary memory device 2230 when programs are executed and can conserve memorized contents even when power supply is cut off. The main memory device 2220 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the main memory device 2220 may include one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block. Through this, characteristics of the main memory device 2220 may be improved. As a consequence, performance characteristics of the system 2200 may be improved.

Also, the main memory device 2220 may further include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off. Unlike this, the main memory device 2220 may not include the semiconductor devices according to the implementations, but may include a static random access memory (SRAM), a dynamic random access memory (DRAM), and so on, of a volatile memory type in which all contents are erased when power supply is cut off.

The auxiliary memory device 2230 is a memory device for storing program codes or data. While the speed of the auxiliary memory device 2230 is slower than the main memory device 2220, the auxiliary memory device 2230 can store a larger amount of data. The auxiliary memory device 2230 may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the auxiliary memory device 2230 may include one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block. Through this, characteristics of the auxiliary memory device 2230 may be improved. As a consequence, performance characteristics of the system 2200 may be improved.

Also, the auxiliary memory device 2230 may further include a data storage system (see the reference numeral 2300 of FIG. 20) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on. Unlike this, the auxiliary memory device 2230 may not include the semiconductor devices according to the implementations, but may include data storage systems (see the reference numeral 2300 of FIG. 20) such as a magnetic tape using magnetism, a magnetic disk, a laser disk using optics, a magneto-optical disc using both magnetism and optics, a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The interface device 2240 may be to perform exchange of commands and data between the system 2200 of the present implementation and an external device. The interface device 2240 may be a keypad, a keyboard, a mouse, a speaker, a mike, a display, various human interface devices (HIDs), a communication device, and so on. The communication device may include a module capable of being connected with a wired network, a module capable of being connected with a wireless network and both of them. The wired network module may include a local area network (LAN), a universal serial bus (USB), an Ethernet, power line communication (PLC), such as various devices which send and receive data through transmit lines, and so on. The wireless network module may include Infrared Data Association (IrDA), code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), a wireless LAN, Zigbee, a ubiquitous sensor network (USN), Bluetooth, radio frequency identification (RFID), long term evolution (LTE), near field communication (NFC), a wireless broadband Internet (Wibro), high speed downlink packet access (HSDPA), wideband CDMA (WCDMA), ultra wideband (UWB), such as various devices which send and receive data without transmit lines, and so on.

FIG. 20 is an example of configuration diagram of a data storage system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 20, a data storage system 2300 may include a storage device 2310 which has a nonvolatile characteristic as a component for storing data, a controller 2320 which controls the storage device 2310, an interface 2330 for connection with an external device, and a temporary storage device 2340 for storing data temporarily. The data storage system 2300 may be a disk type such as a hard disk drive (HDD), a compact disc read only memory (CDROM), a digital versatile disc (DVD), a solid state disk (SSD), and so on, and a card type such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The storage device 2310 may include a nonvolatile memory which stores data semi-permanently. The nonvolatile memory may include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on.

The controller 2320 may control exchange of data between the storage device 2310 and the interface 2330. To this end, the controller 2320 may include a processor 2321 for performing an operation for, processing commands inputted through the interface 2330 from an outside of the data storage system 2300 and so on.

The interface 2330 is to perform exchange of commands and data between the data storage system 2300 and the external device. In the case where the data storage system 2300 is a card type, the interface 2330 may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. In the case where the data storage system 2300 is a disk type, the interface 2330 may be compatible with interfaces, such as IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer Memory Card International Association), a USB (universal serial bus), and so on, or be compatible with the interfaces which are similar to the above mentioned interfaces. The interface 2330 may be compatible with one or more interfaces having a different type from each other.

The temporary storage device 2340 can store data temporarily for efficiently transferring data between the interface 2330 and the storage device 2310 according to diversifications and high performance of an interface with an external device, a controller and a system. The temporary storage device 2340 for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the temporary storage device 2340 may include one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block. Through this, characteristics of the temporary storage device 2340 may be improved. As a consequence, performance characteristics of the system 2300 may be improved.

FIG. 21 is an example of configuration diagram of a memory system implementing memory circuitry based on the disclosed technology.

Referring to FIG. 21, a memory system 2400 may include a memory 2410 which has a nonvolatile characteristic as a component for storing data, a memory controller 2420 which controls the memory 2410, an interface 2430 for connection with an external device, and so on. The memory system 2400 may be a card type such as a solid state disk (SSD), a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on.

The memory 2410 for storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. For example, the memory 2410 may include one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block. Through this, characteristics of the memory 2410 may be improved. As a consequence, performance characteristics of the microprocessor 2400 may be improved.

Through this, the performance of the memory system 2400 may be improved by performing a stable sense and amplification operation.

Also, the memory 2410 according to the present implementation may further include a ROM (read only memory), a NOR flash memory, a NAND flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

The memory controller 2420 may control exchange of data between the memory 2410 and the interface 2430. To this end, the memory controller 2420 may include a processor 2421 for performing an operation for and processing commands inputted through the interface 2430 from an outside of the memory system 2400.

The interface 2430 is to perform exchange of commands and data between the memory system 2400 and the external device. The interface 2430 may be compatible with interfaces which are used in devices, such as a USB memory (universal serial bus memory), a secure digital (SD) card, a mini secure digital (mSD) card, a micro secure digital (micro SD) card, a secure digital high capacity (SDHC) card, a memory stick card, a smart media (SM) card, a multimedia card (MMC), an embedded MMC (eMMC), a compact flash (CF) card, and so on, or be compatible with interfaces which are used in devices similar to the above mentioned devices. The interface 2430 may be compatible with one or more interfaces having a different type from each other.

The memory system 2400 according to the present implementation may further include a buffer memory 2440 for efficiently transferring data between the interface 2430 and the memory 2410 according to diversification and high performance of an interface with an external device, a memory controller and a memory system. For example, the buffer memory 2440 for temporarily storing data may include one or more of the above-described semiconductor devices in accordance with the implementations. The buffer memory 2440 may include one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block. Through this, characteristics of the buffer memory 2440 may be improved. As a consequence, performance characteristics of the microprocessor 2400 may be improved.

Moreover, the buffer memory 2440 according to the present implementation may further include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic. Unlike this, the buffer memory 2440 may not include the semiconductor devices according to the implementations, but may include an SRAM (static random access memory), a DRAM (dynamic random access memory), and so on, which have a volatile characteristic, and a phase change random access memory (PRAM), a resistive random access memory (RRAM), a spin transfer torque random access memory (STTRAM), a magnetic random access memory (MRAM), and so on, which have a nonvolatile characteristic.

As is apparent from the above descriptions, in the semiconductor device and the method for fabricating the same in accordance with the implementations, patterning of a resistance variable element is easy, and it is possible to secure the characteristics of the resistance variable element.

Features in the above examples of electronic devices or systems in FIGS. 17-21 based on the memory devices disclosed in this document may be implemented in various devices, systems or applications. Some examples include mobile phones or other portable communication devices, tablet computers, notebook or laptop computers, game machines, smart TV sets, TV set top boxes, multimedia servers, digital cameras with or without wireless communication functions, wrist watches or other wearable devices with wireless communication capabilities.

While this present document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve described results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments. Only a few implementations and examples are described. Other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document. 

What is claimed is:
 1. An electronic device including a semiconductor memory, the semiconductor memory comprising: one or more resistive storage cells each structured to exhibit different resistance values for storing data; a reference resistance block including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a data sensing block electrically coupled to the one or more resistive storage cells and the reference resistance block and operable to compare a resistance value of a resistive storage cell selected among the one or more resistive storage cells and a reference resistance value of the reference resistance block to determine data stored in the selected resistive storage cell; and a reference resistance adjustment block coupled to the reference resistance block and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust the resistance value of the reference resistance block.
 2. The electronic device according to claim 1, wherein the data sensing block includes a first input terminal through which a read current flows to the selected resistive storage cell and a second input terminal through which a reference current flows to the reference resistance block.
 3. The electronic device according to claim 1, wherein the first gate voltage includes a bias voltage, and wherein the second gate voltage includes an adjustment voltage adjusted depending on a temperature.
 4. The electronic device according to claim 1, wherein the first gate voltage includes a first adjustment voltage adjusted depending on a temperature, and wherein the second gate voltage includes a second adjustment voltage adjusted depending on a temperature.
 5. The electronic device according to claim 3, wherein the reference resistance adjustment block comprises: a voltage generation unit structured to generate a voltage of which level is adjusted depending on a temperature; and a trimming unit coupled to the voltage generation unit to receive the voltage and operable to generate the adjustment voltage by dividing the voltage by a division ratio that is determined based on voltage adjustment codes.
 6. The electronic device according to claim 4, wherein the reference resistance adjustment block comprises: a first voltage generation unit to generate a first voltage of which level is adjusted depending on a temperature; a first trimming unit coupled to the first voltage generation unit to receive the first voltage and to generate the first adjustment voltage by dividing the first voltage by a first division ratio that is determined based on first voltage adjustment codes; a second voltage generation unit to generate a second voltage of which level is adjusted depending on a temperature; and a second trimming unit coupled to the second voltage generation unit to receive the second voltage and to generate the second adjustment voltage by dividing the second voltage by a second division ratio that is determined based on second voltage adjustment codes.
 7. The electronic device according to claim 1, wherein the semiconductor memory further comprises: first and second transistors coupled in series between the first input terminal and the one or more resistive storage cells, and turned on or off in response to a read enable signal and a clamp signal, respectively; and third and fourth transistors coupled in series between the second input terminal and the reference resistance block, and turned on or off in response to the read enable signal and the clamp signal, respectively.
 8. The electronic device according to claim 1, wherein the reference resistance block further includes at least one third reference resistance transistor, and wherein the first reference resistance transistor, the second reference resistance transistor and the third reference resistance transistor are coupled in series, and wherein the reference resistance adjustment block provides a third gate voltage to the third reference resistance transistor.
 9. The electronic device according to claim 8, wherein the first gate voltage includes a first adjustment voltage adjusted depending on a temperature, and wherein the second gate voltage includes a second adjustment voltage adjusted depending on a temperature, and wherein the third gate voltage includes a bias voltage.
 10. The electronic device of claim 1, further comprising a microprocessor which includes: a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; an operation unit configured to perform an operation based on a result that the control unit decodes the command; and a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, wherein the semiconductor memory is part of the memory unit in the microprocessor.
 11. The electronic device of claim 1, further comprising a processor which includes: a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit, wherein the semiconductor memory is part of the cache memory unit in the processor.
 12. The electronic device of claim 1, further comprising a processing system which includes: a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; an auxiliary memory device configured to store a program for decoding the command and the information; a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.
 13. The electronic device of claim 1, further comprising a data storage system which includes: a storage device configured to store data and conserve stored data regardless of power supply; a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.
 14. The electronic device of claim 1, further comprising a memory system which includes: a memory configured to store data and conserve stored data regardless of power supply; a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; a buffer memory configured to buffer data exchanged between the memory and the outside; and an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.
 15. An electronic device including a semiconductor memory, the semiconductor memory comprising: a plurality of bit lines and a plurality of source lines; a plurality of resistive storage cells coupled between a corresponding bit line and a corresponding source line among the plurality of bit lines and the plurality of source lines; a plurality of reference bit lines and a plurality of reference source lines; a plurality of reference resistance blocks coupled between a corresponding reference bit line and a corresponding reference source line among the plurality of reference bit lines and the plurality of reference source lines, and each including at least one first reference resistance transistor and at least one second reference resistance transistor that are coupled in series; a plurality of data sensing blocks each comparing a read current flowing through a corresponding bit line among the plurality of bit lines and a reference current flowing through a corresponding reference bit line among the plurality of reference bit lines to determine data stored in a resistive storage cell selected among a plurality of resistive storage cells coupled to the corresponding bit line; and a reference resistance adjustment block coupled to the reference resistance blocks and operable to provide a first gate voltage to the first reference resistance transistor and a second gate voltage to the second reference resistance transistor and adjust resistance values of the reference resistance blocks.
 16. The electronic device according to claim 15, wherein the plurality of data sensing blocks comprise first and second input terminals, and wherein the semiconductor memory further comprises: a plurality of first and second transistors coupled in series between the first input terminals of the data sensing blocks and the bit lines, and turned on or off in response to a read enable signal and a clamp signal, respectively; and a plurality of third and fourth transistors coupled in series between the second input terminals of the data sensing blocks and the reference bit lines, and turned on or off in response to the read enable signal and the clamp signal, respectively.
 17. The electronic device according to claim 15, wherein the first gate voltage includes a bias voltage, and wherein the second gate voltage includes an adjustment voltage adjusted depending on a temperature.
 18. The electronic device according to claim 15, wherein the first gate voltage includes a first adjustment voltage adjusted depending on a temperature, and wherein the second gate voltage includes a second adjustment voltage adjusted depending on a temperature.
 19. The electronic device according to claim 17, wherein the reference resistance adjustment block comprises: a voltage generation unit to a voltage of which level is adjusted depending on a temperature; and a trimming unit coupled to the voltage generation unit to receive the voltage and operable to generate the adjustment voltage by dividing the voltage by a division ratio that is determined based on voltage adjustment codes.
 20. The electronic device according to claim 18, wherein each reference resistance adjustment block comprises: a first voltage generation unit operable to generate a first voltage of which level is adjusted depending on a temperature; a first trimming unit coupled to the first voltage generation unit to receive the first voltage and operable to generate the first adjustment voltage by dividing the first voltage by a division ratio that is determined based on first voltage adjustment codes; a second voltage generation unit operable to generate a second voltage of which level is adjusted depending on a temperature; and a second trimming unit coupled to the second voltage generation unit to receive the second voltage and operable to generate the second adjustment voltage by dividing the second voltage by a division ratio that is determined based on second voltage adjustment codes.
 21. The electronic device according to claim 15, wherein each reference resistance block further comprises at least one third reference resistance transistor, and wherein the first reference resistance transistor, the second reference resistance transistor and the third reference resistance transistor are coupled in series, and wherein the reference resistance adjustment block provides a third gate voltage to the third reference resistance transistor.
 22. The electronic device according to claim 21, wherein the first gate voltage includes a first adjustment voltage adjusted depending on a temperature, and wherein the second gate voltage includes a second adjustment voltage adjusted depending on a temperature, and wherein the third gate voltage includes a bias voltage. 